Detailed Programme of the ACSD 2003 Conference
Wednesday, 18th June 2003
08.00-08.45: Registration
08.45-09.00: Opening session
09.00-10.00: Invited talk
The Reality of System Design Today: Do Theory and Practice meet?
Grant Martin (PDF)
10.00-10.30: Coffee break
10.30-12.30: Session 1
Polychrony for Formal Refinement-Checking in a System-Level Design Methodology
J.-P. Talpin, P. Le Guernic, S. Kumar Shukla, R. Gupta, and F. Doucet
Case Studies of Model Checking for Embedded System Designs
X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe
Quasi-Static Scheduling for Concurrent Architectures
J. Cortadella, A. Kondratyev, L. Lavagno, and Y. Watanabe
Synthesis of Open Reactive Systems from Scenario-Based Specifications
Y. Bontemps and P.-Y. Schobbens
12.30-14.00: Lunch
14.00-15.30: Session 2
Detecting State Coding Conflicts in STG Unfoldings Using SAT
V. Khomenko, M. Koutny, and A. Yakovlev
A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs
J. Esparza
Separation of Concerns in the Formal Design of Real-Time Shared Data-Space Systems
M. R. Mousavi, M. Reniers, T. Basten, and M. Chaudron
15.30-16.00: Coffee break
16.00-17.15: Tool Session 1
C-Sim Version 5.0
R. Jokl and S. Racek
ABTOOLS: Another B Tool
J.-L. Boulanger
Rialto Profile in the SMW Toolkit
D. Björklund, J. Lilius, and I. Porres
HiWorD: A Petri Net-Based Hierarchical Workflow Designer
B. Benatallah, P. Chrzastowski-Wachtel, R. Hamadi, M. O’Dell, and A. Susanto
CAST—A Task-Level Concurrency Analysis Tool
S. Stuijk, T. Basten, and J. Ypma
17.30-18.30: IFIP Special Interest Group on Embedded Systems
(SIG-ES) Meeting
18.45: Coaches leave for the Welcome Reception at IEC (City of Braga)
22.00: Coaches return
Thursday, 19th June 2003
09.00-10.00: Invited talk
Cyclic Communicating Processes: Abstraction, Hierarchy and Verification
P.S. Thiagarajan (PDF)
10.00-10.30: Coffee break
10.30-12.30: Session 4
Modelling a Secure, Mobile, and Transactional System with CO-OPN
D. Buchs, S. Chachkov, and D. Hurzeler
Developing a Formal Specification for the Mission System of a Maritime Surveillance Aircraft
L. Petrucci, J. Billington, L. M. Kristensen, and Z. H. Qureshi
Design Validation of ZCSP with SPIN
V. Beaudenon, E. Encrenaz, and J.-L. Desbarbieux
Memory Fault Tolerance Software Mechanisms: Design and Configuration Support Through SWN Models
P. Ballarini, L. Capra, G. Franceschinis, and M. De Pierro
12.30-14.00: Lunch
14.00-15.30: Session 5
Component-Based Design: Towards Guided Composition
S. Moschoyiannis and M. W. Shields
Compositional High Level Petri Nets with Timing Constraints — A Comparison
E. Pelz and H. Fleischhack
Compositional Verification of Integrity for Digital Stream Signature Protocols
R. Gorrieri, F. Martinelli, M. Petrocchi, and A. Vaccarelli
15.30-16.00: Coffee break
16.00-17.30: Tool Session 2
A Framework for the Development of Protocols
F. Crazzolara and G. Milicia
BHDL: Circuit Design in B
A. Aljer, P. Devienne, S. Tison, J.-L. Boulanger, and G. Mariano
CONFRES: Interactive Coding Conflict Resolver Based on Core Visualisation
A. Madalinski
Abstract Model Checking and Refinement of Temporal Logic in aSPIN
M. del Mar Gallardo, J. Martínez, P. Merino, and E. Pimentel
VoDkaV Tool: Model Checking for Extracting Global Scheduler Properties from Local Restrictions
J. J. Sánchez Penas and T. Arts
AutoFOCUS and the MoDe Tool
J. Romberg, J. Jürjens, G. Wimmel, O. Slotosch, and G. Hahn
17.45: Coaches leave for the Conference Banquet at Pousada de Santa Marinha (City of Guimaraes)
23.00: Coaches return
Friday, 20th June 2003
09.00-10.00: Invited talk
Model Driven Embedded Systems
Ian Oliver (PDF)
10.00-10.30: Coffee break
10.30-12.30: Session 7
Merging State-Based and Action-Based Verification
H. Hansen, H. Virtanen, and A. Valmari
Communicating Transaction Processes
A. Roychoudhury and P. S. Thiagarajan
Logic of Involved Variables—System Specification with Temporal Logic of Distributed Actions
A. Alexander and W. Reisig
Modifying Petri Net Models by Means of Crosscutting Operations
J. P. Barros and L. Gomes
12.30-14.00: Lunch
14.00-16.00: Session 8
Specification Coverage Aided Test Selection
T. Pyhälä and K. Heljanko
Verification of JavaSpaces™ Parallel Programs
J. van de Pol and M. Valero Espada
On Lifting of Statechart Structuring Mechanisms
L. Gomes and A. Costa
A New Synchronization in Finite Stochastic Petri Box Calculus
H. Macià, V. Valero, F. Cuartero, and F. L. Pelayo
16.00: Closing session
Saturday, 21th June 2003
07.45: Coaches leave for the excursion
09.00: Coaches arrive at Porto
09.30: Boat leaves for the excursion
11.30: Port wine aperitive served on board
12.00: Lunch served on board
16.00: Boat arrives at Peso da Régua
16.30: Visit to a Port wine state with a Port wine tasting
17.40: Train (Bus) departs from Peso da Régua
20.00: Coaches leave for Braga
21.15: Coaches arrive at Braga
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